1. Field of the Invention
The present invention relates to semiconductor packages, and, more particularly, to a semiconductor package having through silicon vias (TSV), a method of fabricating the semiconductor package, and an interposer structure of the semiconductor package.
2. Description of Related Art
Flip-chip technologies facilitate to reduce chip packaging sizes and shorten signal transmission paths and therefore have been widely used for chip packaging. Various types of packages, such as chip scale packages (CSP), direct chip attached (DCA) packages and multi-chip module (MCM) packages, can be achieved through flip-chip technologies.
In a flip-chip packaging process, a great coefficient of thermal expansion (CTE) mismatch between a chip and a packaging substrate adversely affects the formation of joints between conductive bumps of the chip and contacts of the packaging substrate, thus likely resulting in delamination of the conductive bumps from the packaging substrate. On the other hand, along with increased integration of integrated circuits, a CTE mismatch between a chip and a packaging substrate induces more thermal stresses and leads to more serious warpage, thereby reducing the product reliability and resulting in failure of a reliability test.
To overcome the above-described drawbacks, a silicon interposer is disposed between a semiconductor chip and a packaging substrate. Since the silicon interposer and the semiconductor chip are made of similar materials, the above-described drawbacks caused by a CTE mismatch can be effectively prevented.
FIGS. 1A to 1C show a method of fabricating a conventional semiconductor package 1.
Referring to FIG. 1A, a plurality of TSVs 100 are formed in a silicon interposer 10, and a redistribution layer (RDL) structure (not shown) is formed on an upper side of the silicon interposer 10. A plurality of semiconductor chips 11 are disposed on the upper side of the silicon interposer 10 and electrically connected to the TSVs 100 through a plurality of conductive bumps 110.
Referring to FIG. 1B, an encapsulant 12 is formed on the silicon interposer 10 to encapsulate the semiconductor chips 11, thereby forming a plurality of packages 1a. 
Referring to FIG. 1C, an RDL structure 13 is formed on a lower side of the silicon interposer 10 according to the practical need, and then a singulation process is performed to obtain a plurality of singulated packages 1a. Each of the packages 1a is disposed on and electrically connected to a packaging substrate 15 through a plurality of conductive bumps 14.
However, forming the through silicon vias 100 in the silicon interposer 10 results in a high fabrication cost. Further, according to the process yield, some units 10′ of the silicon interposer 10 may be inferior. Although a good semiconductor chip 11 can be selected by performing an electrical performance test after a singulation process, the good semiconductor chip 11 may be disposed on an inferior unit 10′. As such, the finished package 1a cannot pass a reliability test, and consequently the good semiconductor chip 11 must be wasted along with the inferior unit 10′, thereby increasing the fabrication cost.
On the other hand, if inferior units 10′ are detected before forming the encapsulant 12 so as to avoid disposing of good semiconductor chips 11 on the inferior units 10′, it will become difficult to control the amount and flow path of the encapsulant 12. Consequently, the semiconductor chips 11 cannot be evenly covered by the encapsulant 12.
In addition, since the silicon interposer 10 is not singulated before disposing the semiconductor chips 11 on the silicon interposer 10, the semiconductor chips 11 are required to be less in size than the corresponding units 10′, such that the number of the electrodes of the semiconductor chips 11 is limited. Consequently, the module function and efficiency of the units 10′ are limited.
Therefore, how to overcome the above-described drawbacks has become urgent.